Two types of memory devices are commonly used in the field of data storage. The first type is volatile memory in which stored information is lost when power is removed. The second type is non-volatile memory in which the information is preserved after the power is removed. Non-volatile memory may be designed for multiple programming or for one-time programming. Examples of multiple programmable non-volatile memory include electrically erasable programmable read only memories (EEPROMs) and flash memory. Unlike a multiple programmable memory, a one-time programmable non-volatile memory can be programmed only once. The programming typically involves the “blowing” of a fuse element of the cell. The programming of a one-time programmable memory is irreversible.
One type of existing one-time programmable memory is a single-ended latch-based memory. In the existing single-ended latch-based memory, a latching amplifier compares a reference voltage, typically set to a percentage of the supply voltage, against a fuse with a current source. If the fuse is not programmed, the current source drives the voltage on the fuse to the supply voltage and the latching amplifier outputs a “0.” If the fuse is programmed, the fuse sinks the current and the voltage level goes to ground, causing the latching amplifier to output a “1.” Because the reference is a percentage of the supply voltage, the read margin of the single-ended latch-based memory cells is reduced resulting in reduced yield and manufacturability for these memory cells.
Furthermore, many modern applications require the secure storage of large amounts of data in non-volatile memories. Because of the nature of the information required in these secure applications, the ability to output a random value on power-up is critical. Because the unprogrammed output of the single-ended latch based memory cells is set to a default value, the use of these memory cells in certain secure applications may not be appropriate.
What is therefore needed is a latch-based one time programmable memory cell with increased read margin, yield, and manufacturability.
What is further needed is a secure latch-based one time programmable memory cell providing random output during power up.